This application claims priority benefits to European Patent Application Number 99870110.6 filed on Jun. 1, 1999.
The present invention is related to a semiconductor device and a circuit for electrostatic discharge and overvoltage protection applications.
Electronic devices and circuits are to be protected against damage arising from electrostatic discharge pulses, current transients or overvoltage levels. Protection devices or circuits using silicon controlled rectifier structures (SCR) are known in the art. SCR devices were applied frequently as an efficient electrostatic discharge protection clamp. These devices are made such that as a result of electrostatic discharge (ESD) pulses, current transients or overvoltage levels, an n-p-n-p thyristor structure is triggered thereby ensuring the clamping of the ESD-pulses, and snapback of the device to very low holding voltages. These devices furthermore are such that this absorption of electrostatic discharge pulses, current transients or overvoltage levels leads to low power dissipation after triggering. Examples of such SCR devices are disclosed in the U.S. Pat. Nos. 5,072,273, 5,343,053 and 5,663,860.
A cross-section of a prior art classical SCR-device is shown on FIG. 1. The SCR-device is fabricated in a semiconductor substrate 12 of a p-type conductivity with a n-well 11 therein. In the figure, the pad connection 17 is connected to both the n-well contact region 13 and a p+-region 14 inside the n-well. The ground is connected to the p-substrate contact region 16 and an n+-region 15 inside the p-substrate 12. An equivalent circuit schematic is shown in FIG. 2. It comprises a parasitic pnp 299 and a parasitic npn transistor 200 that are connected. The npn-transistor 200 consists of the n-well/p-substrate/n+region, whereas the pnp-transistor 299 consists of the p+-region/n-well/p-substrate.
In normal operating conditions, the SCR-device is off. When a positive ESD-pulse is applied at the pad, the n-well 11 to p-substrate 12 diode 11/12 is reverse biased, until it goes into breakdown. This typically happens at voltages on the order of 40-50V. Once the n-well/substrate diode is in breakdown, electron-hole pairs are generated in the space-charge region of this diode. The holes are flowing to the p-substrate contact 16, whereas the electrons are flowing to the n-well contact 13. Due to the substrate resistance Rsub, the p-base of the parasitic npn transistor 200 is charging up, and when the base voltage is becoming higher than 0.7V, this npn parasitic transistor is triggered. At about the same time, the pnp transistor is triggered due to the charging up phenomenon, and via a positive feedback mechanism, the device is latched into a low impedance state, with a low holding voltage of typically 2-3 Volt, or in some applications 3-4V, and a low series resistance of typical a few Ohm, which leads to very low power dissipation and high ESD-thresholds.
The problem of most of the classical SCR devices is that the trigger voltage at which the device goes into the low-impedance on-state is quite high, typically 50V, which is too high for normal low-voltage technologies. In order to allow the use of SCR-devices but avoid the high trigger voltages, a so-called low-voltage triggered SCR (LVTSCR) has been proposed. A cross section of the LVTSCR is shown on FIG. 3, and an equivalent circuit schematic is shown on FIG. 4. In this protection device, an n+region 39 is implanted at the edge between the n-well 31 and the p-substrate 32. The n+-region/p-substrate junction will go into breakdown at a lower voltage, typical 13-14V, in this way lowering the triggering voltage of the SCR. The n+-region can be separated from the n+region in the p-substrate either by a field oxide or by a poly-gate (395, shown in FIG. 3). In the latter case, the gate of the parasitic nMOS is connected to the ground, as is shown on FIGS. 3 and 4. This device is well suited to protect technologies with normal operating voltages.
The classical SCR protection devices are typically suited for high voltage applications, whereas the LVTSCR structure is frequently used for normal operating voltage applications. For some applications, however, the low trigger voltage (for instance of 14V) for an LVTSCR is too low, whereas the high trigger voltage (for instance of 50V) for the classical SCR is too high. As a result, there is a need for SCR-structures that trigger at intermediate voltages, or for which the trigger voltage can be adapted, depending on the application.
The present invention aims to fill this gap in protection devices. The present invention discloses a semiconductor device for electrostatic discharge or overvoltage protection applications, said device comprising means for absorbing an electrostatic discharge pulse or an overvoltage level, said means being triggered at intermediate voltages.
The present invention furthermore discloses a semiconductor device for electrostatic discharge or overvoltage protection applications, said device comprising means for absorbing an electrostatic discharge pulse or an overvoltage level, said means being triggered at intermediate voltages and said means being extendable with a third trigger component and possibly further trigger components, the addition of said third and further trigger components extending sequentially the range of the intermediate trigger voltages such that the protection trigger voltage can be adapted depending on the application.
In a first aspect of the present invention, a semiconductor device for electrostatic discharge or overvoltage protection applications is disclosed, said device comprising means for absorbing an electrostatic discharge pulse or an overvoltage level, said means being triggered at intermediate voltages and said means including a series configuration of at least two trigger components. Said means can further be extended with a third trigger component and possibly further trigger components in said series configuration, the addition of said third and further trigger components extending sequentially the range of the intermediate trigger voltages. Said trigger components can comprise components, preferably diodes, with a specific breakdown voltage, the sum of the breakdown voltages of said diodes defining the specific intermediate trigger voltage of said device.
In another embodiment of the device of the invention according to the first aspect, the device can further comprise an integrated circuit having a functionality and an impedance being in the connection of said means to said circuit. The impedance can be replaced by any means being adapted for building up a voltage drop. The impedance preferably is a resistor. Said circuit further comprises components or has components in parallel or connected to the circuit, components that convert an overvoltage level or an electrostatic discharge pulse of an intermediate level into an electrical current, said current creating a voltage of an intermediate level over said impedance, said voltage triggering said means such that said overvoltage level or electrostatic discharge pulse is absorbed.
For the purpose of this patent application, the following terms are introduced here. A trigger component, or triggering component, has the meaning that in the devices of the invention, at least one component or the triggering component is made such that as a result of electrostatic discharge (ESD) pulses, current transients or overvoltage levels, this component is triggered thereby ensuring the clamping of the ESD-pulses, and snapback of the device to very low holding voltages. Thus, the electrostatic discharge pulses, current transients or overvoltage levels are absorbed in the device of the invention by making use of the above-introduced trigger components and further in such a way that a low power dissipation occurs in the device after triggering and snapback of the device to the low holding voltages. Low, high and intermediate voltages are to be understood in the context of a specific protection application for a specific technology. The terms low, high and intermediate voltage levels refer to overvoltage levels or to voltage levels resulting from electrostatic discharge pulses. Such voltages are higher than the normal operating voltages of electronic systems and can be classified in terms of high, intermediate and low overvoltage levels, the specific voltage values corresponding to high, low and intermediate being dependent on the specific technology. For the mainstream applications (for example a 0.7 xcexcm CMOS technology), the normal operating voltages are of the order of 5-12 Volt. A high overvoltage level is than referred to as about 40-50 Volt. A low overvoltage level is referred to as of the order of 14 Volt. Intermediate overvoltage levels are levels therebetween. Thus, the specific values of the terms low, high and intermediate overvoltage levels depend on the specific application, specifically on the values of the normal operating voltages of the specific technology. It is known in the art that the normal operating voltages for instance a 0.25 xcexcm CMOS technology are lower than 5-12 Volt. Thus the value of a low overvoltage level may also be lower than 14 Volt and the value of a high overvoltage level may also be lower than or equal to, or even be higher than 50 Volt.
In a second aspect of the present invention, a semiconductor device for electrostatic discharge or overvoltage protection applications is disclosed, said device comprising a first region of a first conductivity type in a semiconducting substrate of a second conductivity type and at least two separated regions of said second conductivity type being within said first region, said separated regions of said second conductivity type not abutting the substrate region of said second conductivity type. The device further comprises at least two separated regions of said first conductivity type being within said substrate, said separated regions of said first conductivity type not abutting said first region; and a connection inbetween at least one of said separated regions of said second conductivity type within said first region and at least one of said separated regions of said first conductivity type within said substrate.
The connection is such that said device is absorbing an electrostatic discharge pulse or an overvoltage level at an intermediate voltage level. In a first embodiment of this second aspect of the invention, said connection can be a low-resistive connection, preferably a metal line, and preferably external to said first region and to said substrate. In a second embodiment, said connection can comprise at least one component having a breakdown voltage, said component being in series with said separated regions of said second conductivity type and said separated regions of said first conductivity type. According to this second embodiment of the invention, said connection can comprise at least one region of said first and/or at least one region of said second conductivity type, said regions being within a second region of either one of said conductivity types, the second region being of the other (second or first) conductivity type than the embedded region (of a first or second conductivity type resp.). One of these regions in the second region can be present as a contact region. Additional regions can be embedded within said second region. Preferably, this second region is within said substrate and is of said first conductivity type. At least part of the regions that are embedded within said second region are connected to the separated regions in the first region and in the substrate. Specifically, one region of said first conductivity (one region of these embedded regions in the second region) can be directly connected with a low-resistive connection to one of the separated regions of said second conductivity type in the first region. Furthermore, one region of said second conductivity type of these embedded regions can be directly connected with a low-resistive connection to one of the separated regions of said first conductivity type in said substrate.
In the device of the invention, the regions of at least one of the set of said separated regions can be separated by an insulating material, said material preferably comprising an oxide material. The separated regions can also be separated by a control terminal overlying said substrate or said first region with an insulating material therebetween. One region of at least one of the set of said separated regions can be directly connected to the control terminal of said one set.
In the device of the invention according to the second aspect of the invention, said first region of said first conductivity type can be connected to a pad contact and said substrate of said second conductivity type is connected to ground, the connections to said pad contact and to ground preferably being via a highly doped contact region in said first region and said substrate respectively. It is evident that the reverse configuration can be made as well: said first region of said first conductivity type being connected to ground and said substrate of said second conductivity type being connected to a pad contact. A pad contact is the bonding pad connection of the device to the external devices or structures. Preferably, it is an Input/Output pad, or the connection to the package of the device, or the connection to the programming pin for fuses, or the connection to the supply voltage.
In an embodiment of the invention, the device of the invention can be integrated within said substrate with an integrated circuit having a functionality and that needs to be protected against overvoltage levels or electrostatic discharge pulses. The connection to such integrated circuit can also be done via the bonding pad.
In a third aspect of the invention, a protection circuit for electrostatic discharge or overvoltage protection applications is disclosed, said circuit comprising at least two, preferably MOS, transistors in series, said transistors having at least two electrodes and one control terminal, one electrode of the first transistor being connected to one electrode of the second transistor, the other electrode of said transistors being connected to the respective control terminals of said transistors. Said transistors preferably are of the opposite type and one control terminal of one transistor can be grounded while the control terminal of the second transistor is connected to a pad contact.
In another embodiment of this third aspect of the invention, one electrode of the first transistor is directly connected to the one electrode of the second transistor. An additional junction of first and second conductivity type regions can be present inbetween the one electrode of the first transistor and the one electrode of the second transistor.
Yet, all combinations of the different embodiments according to different aspects of the invention are feasible.